The present invention relates to a technology for controlling a slew rate of an output driver for outputting data or signals, depending on a temperature in any of a variety of semiconductor devices such as a semiconductor memory device.
An output driver serves to output data or signals to the outside of a chip in any of a variety of semiconductor devices such as a semiconductor memory device or the like.
FIG. 1 is a block diagram of an output driver of a conventional semiconductor device.
Referring to FIG. 1, an output driver includes a pre-driver 110 and a main driver 120.
The pre-driver 110 generates at least one driving control signal for driving a main driver 120 in accordance with a logic level of data DATA that will be output by the output driver. The pre-driver 110 generates two driving control signals: a pull-up driving control signal UP_PRE that controls the main driver 120 such that the main driver 120 pulls up an input/output node DQ and a pull-down driving control signal DN_PRE that controls the main driver 120, such that the main driver 323 pulls down the input/output node DQ. The drain and supply voltages are denoted by VDDQ and VSSQ respectively.
The pull-up driving control signal UP_PRE is activated when the data DATA that will be output by the output driver has a logic high level so that the main driver 120 outputs the data DATA having the logic high level by pulling up the input/output node DQ. Since a pull-up driver 121 of the main driver 120 is generally implanted with a P-channel metal oxide semiconductor (PMOS) transistor, the activation of the pull-up driving control signal UP_PRE means that the pull-up driving control signal UP_PRE is at a logic low level.
The pull-down driving control signal DN_PRE is activated when the data DATA that will be output by the output driver has a logic low level so that the main driver 120 outputs the data having the logic low level by pulling down the input/output node DQ. Since a pull-down driver 122 of the main driver 120 is generally implemented with an N-channel metal oxide semiconductor (NMOS) transistor, the activation of the pull-down driving control signal UP_PRE means that the pull-down driving control signal UP_PRE is at a logic high level.
When the data having the logic high level are output, the pre-driver 110 activates the pull-up driving control signal UP_PRE to the logic low level and deactivates the pull-down driving control signal DN_PRE to the logic low level. When the data having the logic low level is output, the pre-driver 110 deactivates the pull-up driving control signal UP_PRE to the logic high level and activates the pull-down driving signal DN_PRE to the logic high level. When no data is output, the pre-driver 110 deactivates the pull-up driving control signal UP_PRE to the logic high level and deactivates the pull-down driving control signal DN_PRE to the logic low level to allow the input/output node DQ to be in a high state.
The main driver 120 outputs the data having a logic high or low level by pulling up or pulling down the input/output node DQ in response to the driving control signals UP_PRE and DN_PRE. In more detail, when the pull-up driving control signal UP_PRE is activated, the main driver 120 pulls up the input/output node DQ to output the data having the logic high level. When the pull-down driving control signal DN_PRE is activated, the main driver 120 pulls down the input/output node DQ to output the data having the logic low level. Although each of the pull-up and pull-down drivers 121 and 122 implemented with one transistor is illustrated in FIG. 1, the main driver 120 may include a plurality of transistors connected in parallel.
A slew rate is an amount of a voltage that changes per hour, i.e., a gradient of a voltage change. The slow rate is an important value in an input/output circuit such as the output driver. In order to stably output the data to the outside of the chip, the output driver has to have a uniform slew rate.
When a temperature of the semiconductor device is varied, properties of a variety of transistors and a variety of delay circuits in the chip are varied. Generally, when the temperature increases, the slew rate is reduced.
FIG. 2 is a schematic diagram illustrating a variation of a slew rate at the output node DQ of the output driver of FIG. 1 and a size variation of a data window.
The upper side of FIG. 2 illustrates a slew rate and data window at a normal temperature and the lower side of FIG. 2 illustrates a slew rate and data window at a high temperature.
When comparing the upper and lower sides of FIG. 2, the slew rate (gradient) of the output driver is low at the high temperature compared with at the normal temperature. Therefore, a valid data window is reduced at the high temperature.
When the valid data window is reduced, it is difficult to recognize the data output from the output driver at an external side of the chip.